The present invention relates to a semiconductor integrated circuit device and to a method of producing the same. More specifically, the invention relates to technology that can be effectively applied to a semiconductor integrated circuit device having a DRAM (dynamic random access memory).
Memory cells in a DRAM are generally arranged at intersecting points of plural word lines and plural bit lines that are arranged in the form of a matrix on a main surface of a semiconductor substrate. Each memory cell is constituted by a MISFET (metal insulator semiconductor field-effect transistor) that selects it and a data-accumulating capacitor element (capacitor) connected in series with the MISFET.
The MISFET for selecting the memory cell is formed in an active-region surrounded by a device isolation region, and it is constituted chiefly by a gate oxide film, a gate electrode formed integrally with a word line, and a pair of semiconductor regions forming a source and a drain. Two MISFETs are usually formed in one active region, and the source and drain (semiconductor regions) of one of the two MISFETs are shared at the central portion of the active region. A bit line is arranged on the MISFET and is electrically connected to the semiconductor regions that are shared. The capacitor is arranged on the MISFET and is electrically connected to the other source and drain.
In a DRAM having a capacitor-over-bit-line (COB) structure in which the capacitor is arranged on the bit line, the lower electrode (accumulator electrode) of the capacitor arranged on the bit line is formed to have a cylindrical shape, and a capacitor insulating film and an upper electrode (plate electrode) are formed on the lower electrode. The lower electrode is formed to have a cylindrical shape to increase the surface area thereof, in an attempt to compensate for a reduction in the electric charge (Cs) accumulated in the capacitor caused by the fact that the memory cell is finely formed. In the memory cell having a COB structure as described above, the capacitor must be constructed to have a three-dimensional structure to a conspicuous degree from the standpoint of maintaining reliable operation as a semiconductor memory device.
Even by constructing the capacitor to have a three-dimensional structure, a difficulty can be expected in maintaining the required capacitance (accumulated electric charge) in modern integrated semiconductor devices and, particularly, in the DRAMs produced after those corresponding to 256 Mbits (megabits).
A study has been made of the use of a highly dielectric material (ferroelectric material), such as tantalum oxide (Ta2O5), STO (SrTiO3) or BST (BaxSr1xe2x88x92xTiO3), as an insulating film for a capacitor, as described in xe2x80x9cApplied Physicsxe2x80x9d, Vol. 65, No. 11, published by Japanese Academy of Applied Physics, Nov. 10, 1996, pp. 1111-1112. Ta2O5 has a specific inductive capacity of as high as about 40, and STO and BST have specific inductive capacities that are very high, such as about 200 to 500. By using these films having high specific inductive capacities, therefore, it becomes easy to realize a large capacity compared to use of the traditionally used silicon oxide film and silicon nitride film. In particular, STO and BST exhibit high dielectric constants, and a greatly increased capacity can be expected.
The lower electrode of the capacitor is connected to the source and drain of the MISFET through a plug, and a reaction-preventing layer is formed for preventing the reaction of ruthenium forming the lower electrode with a plug material (silicon).
When a DRAM having the above structure is highly densely integrated, however, there occurs a problem of deviation in matching relative to an underlying silicon plug at the time of patterning the lower electrode of the capacitor. That is, in the highly dense DRAMs produced after the 256-megabit DRAM, the size of the silicon plug in the transverse direction is nearly equal to the size of the lower electrode in the transverse direction. In such a dimensional region, the pattern of the lower electrode is deviated relative to the underlying pattern (silicon plug) at the time of effecting the patterning for forming the lower electrode, relying upon photolithography. Due to this deviation in matching, the plug member is partly exposed. The presence of the exposed portion permits the dielectric (capacitor-insulating film) to come into direct contact with the plug member, whereby a leakage current increases, making it no longer possible to accomplish a desired insulation property,. This will be described in further detail with reference to FIGS. 60(a) to 62(c).
FIGS. 58(a) to 58(c) illustrate the case of a dimensional balance in a DRAM developed before the 64-M DRAM. In this case, there is a margin in the size of the lower electrode relative to the size of the plug, so that some degree of deviation in matching causes no problem. A ruthenium film 402 is formed on the whole surface of an Si plug 401, and a photoresist film 403 is patterned by photolithography (FIG. 58(a)). Here, the photoresist film 403 is formed such that it is deviated by a distance d from an ideal patterning position (indicated by dotted lines). The ruthenium film 402 is machined by anisotropic dry-etching to form a lower electrode 404 of ruthenium (FIG. 58(b)). The photoresist film 403 is removed, a dielectric film 405 is formed (FIG. 58(c)), and, then, an upper ruthenium electrode is formed. Here, the size of the lower electrode 404 has a margin relative to the plug 401. Therefore, the Si plug 401 is not exposed in machining the ruthenium film 402 to form the lower electrode 404.
Referring to FIGS. 59(a) and 59(b), on the other hand, when the size of the plug becomes close to the size of the lower electrode, a deviation in matching occurs, which is a problem to be solved by this invention. The Si plug 407 is formed at a predetermined position in the insulating film 406, and a lower ruthenium electrode 408 is formed in the same manner as in FIG. 59(a). Here, the lower electrode 408 is formed such that it is deviated by a distance d from an ideal pattern position (indicated by dotted lines). The size of the lower electrode 408 is equal to the size of the plug 407; and, hence, the Si plug 407 is partly exposed due to a deviation in matching by the distance d (portion indicated by an arrow A in FIG. 59(a)). A dielectric film 409 formed in this state (FIG. 59(b)) is brought into direct contact with the Si plug 407 (portion in the circle B in FIG. 59(b)), and the dielectric strength of the dielectric film 409 decreases at the portion B, whereby a leakage current increases, making it no longer possible to maintain the memory function.
FIGS. 60(a) to 60(c) illustrate a case where a silicide film is provided to prevent a thermal reaction between ruthenium, used as the lower electrode, and the Si plug. After an Si plug 411 is formed in a predetermined region of the insulating film 410, a silicide film 412 is formed on the surface thereof, and a ruthenium film 413 is formed on the whole surface thereof (FIG. 60(a)). The ruthenium film 413 is machined by the method mentioned above to form a lower electrode 414 (FIG. 60(b)). In this case, too, deviation occurs in the matching by a distance d, and the Si plug 411 is partly exposed (portion indicated by an arrow A in FIG. 60(b)). That is, the silicide film 412, too, is etched at the time of machining the ruthenium film 413, and the Si plug 411 is partly exposed. A dielectric film 415 that is formed in this state comes into direct contact with the Si plug 411 at a portion indicated by circle B in FIG. 60(c). Therefore, the leakage current inevitably increases and it becomes difficult to maintain a normal memory function.
It is therefore an object of this invention to provide a semiconductor integrated circuit device having a structure in which a dielectric (capacitor-insulating film) that is subsequently formed does not come into contact with the underlying plug even when the lower electrode of the capacitor is formed such that it is deviated from the underlying plug, and a method of producing the same.
Another object of this invention is to maintain a desired capacity by forming the lower electrode using ruthenium in a three-dimensional form, by increasing the surface area of the capacitor and by increasing the dielectric constant of the capacitor-insulating film.
A further object of this invention is to form a capacitor-insulating film in plural layers, to increase the life of the capacitor before it is broken down, to decrease drop-out bits of the memory cells and to enhance the reliability of the semiconductor integrated circuit device.
The above and other objects as well as novel features of the invention will become obvious from the description provided in this specification and from the accompanying drawings.
Briefly described below are representative examples of the features of the present invention is disclosed in this application.
The above problem is solved by forming an underlying silicon plug, first covering the whole surface thereof with an insulating film, forming an opening in the insulating film so as to make a connection to the silicon plug, and then forming a silicide film in a self-aligned manner on only the surface of the plug that is exposed in the bottom of the opening.
The opening, i.e., the side wall in the opening, is used as a capacitor region. Upon controlling the thickness of the insulating film forming the opening, therefore, the height of the capacitor is maintained, and, hence, the area of the capacitor can be increased. By using ruthenium as the lower electrode, further, the dielectric constant of the dielectric is not decreased and a desired capacity is maintained.
By using ruthenium as the lower electrode and silicon as the plug, a reaction takes place between the ruthenium and the silicon during heat treatment to form ruthenium silicide. The volume expands while the silicide is being formed causing the shape of the capacitor to become abnormal. The abnormal shape could become a cause of an increase in the leakage current through the dielectric (capacitor-insulating film) Therefore, the silicide film is at least formed prior to forming the dielectric.
Further, a very thin oxide film is formed on the surface of the ruthenium silicide, after the silicide film is formed, but prior to forming the lower electrode of ruthenium. The thin oxide film works to suppress the silicide reaction from reaching the lower electrode. Despite the fact that the heat treatment is effected for crystallizing and reforming the dielectric after the dielectric has been formed, the shape of the capacitor does not become abnormal, and an increase in the leakage current through the capacitor-insulating film (dielectric) is avoided.
The dielectric can be selected from tantalum oxide, titanium oxide, barium strontium titanate, barium titanate and strontium titanate, and can be used in the form of a single-layer film or a laminated-layer film of at least one material, or a laminated-layer film of different materials. In the case of the single-layer film, the leakage current of the capacitor may not finally be suppressed at the time when the semiconductor integrated circuit device is completed. It is therefore desirable to employ a laminated-layer structure from the standpoint of maintaining reliability.
In accordance with this invention, the capacitor must have a three-dimensional structure such that the height of the lower electrode is larger than the size thereof in the transverse direction. When a dielectric is formed to have such a three-dimensional lower electrode structure, the condition must be so selected that the film is formed while maintaining a uniform thickness even on the top of the three-dimensional structure and on the bottom thereof. The film is formed by the CVD method. When the above material is formed by the CVD method, an organometallic compound is used as the starting material. Though the film is formed over a temperature range of from about 350xc2x0 C. to about 500xc2x0 C., organic matters contained in the starting material are inevitably transferred into the film. Further, the dielectric film formed on the lower electrode over the above temperature range becomes amorphous. The impurities that are contained therein and the amorphous structure are detrimental to the stability of the capacitor. In particular, the stability very sensitively fluctuates depending upon the temperature and this makes it difficult to maintain the reliability of the semiconductor integrated circuit device. In order to stabilize the capacitor, the film that is formed is heat-treated so as to be crystallized. This can be accomplished at a temperature of roughly not higher than 750xc2x0 C. though the temperature for crystallization differs depending upon the material of the dielectric and the material of the lower electrode. As the film is crystallized, organic impurities are mostly expelled out of the film. Besides, the film itself becomes dense and does not absorb impurities again even when it is left to stand, unlike that of the amorphous films. Through the crystallization, the capacitor exhibits greatly stabilized properties and does not lose stability even when it is heat-treated at about 400xc2x0 C. in a step of forming wirings after the step of forming the capacitor.
Upon crystallizing the capacitor-insulating film (dielectric) as described above, the capacitor properties are stabilized and the capacitor insulating film exhibits an increased dielectric constant. The crystallization, however, is accompanied by the occurrence of a new problem, which is the formation of grain boundaries where the thickness of the film becomes smaller than that of other portions. As a result, the electric field is concentrated to a conspicuous degree at the grain boundaries and dielectric breakdown tends to occur. This results in a decrease in the long-term reliability required for the semiconductor integrated circuit devices and a decreased value as a product. This problem can be overcome if the film could be transformed into a single crystal instead of being polycrystallized which, however, is difficult to realize. This problem becomes more conspicuous when a thick dielectric of a single layer is crystallized. A decrease in the reliability caused by the grain boundaries can be advantageously prevented by forming the capacitor-insulating film to have a laminated-layer structure. Basically, the grain boundaries may be disconnected among the films neighboring up and down by employing a multi-layer structure even though the grain boundaries may exist. in each film. It is further desired to crystallize thin films, layer by layer, and to stack them. The present inventors have observed the effect of laminated-layer structures of tantalum oxide, relying upon an electric breakdown light-emission method, and have discovered the fact that when the capacitor is formed by crystallizing a single layer having a predetermined thickness, the dielectric breakdown occurs at a given point at all times, but when the capacitor is formed by laminating thin crystallized films up to a predetermined thickness, the capacitor as a whole starts emitting light and the breakdown is concentrated at one point at a last point of breakdown. It is, therefore, obvious that the single-layer film contains many portions where the dielectric breakdown easily occurs, whereas the dielectric film of a multi-layer structure, for preventing the film from becoming thin at the grain boundaries, is very strong against dielectric breakdown. In order to draw out the above effect, further, it is very important to select the upper electrode that is formed on the dielectric in contact therewith and, hence, to select an electrode material that does not trigger a reaction with the dielectric and the conditions of formation.
In accordance with this invention, the upper electrode is formed of ruthenium by the CVD method. Further, titanium nitride can be used when at least tantalum oxide or titanium oxide is formed as the uppermost layer.
Constitutions of the invention will now be described.
The invention is concerned with a method of producing a semiconductor integrated circuit device having a semiconductor region on a main surface of a semiconductor substrate and having a capacitor element that includes a first electrode, a dielectric film and a second electrode in an upper layer on the main surface, comprising the steps of: forming the semiconductor region on the main surface of the semiconductor substrate; forming a first insulating film on the semiconductor region; forming a first electric conductor in the first insulating film; forming a second insulating film on the first insulating film; forming an opening in the second insulating film to expose part of the first electric conductor on the bottom of the opening; forming a barrier film on the surface of the first electric conductor in the opening; forming the first electrode in the opening so as to be electrically connected to the semiconductor region through the barrier film and the first electric conductor; forming the dielectric film on the first electrode; heat-treating the dielectric film in an oxidizing atmosphere; and forming the second electrode on the dielectric film. Here, the semiconductor region may be either a source region o-r a drain region of a MISFET formed on the main surface of the semiconductor substrate.
Further, the second insulating film is constituted by a first insulating film and a second insulating film formed on the first insulating film, and the step of forming the opening includes the steps of: etching the second insulating film under a condition where the rate of etching the second insulating film is larger than the rate of etching the first insulating film; and etching the first insulating film on the bottom in the opening formed in the second insulating film. In this case, the first insulating film is constituted by silicon nitride and the second insulating film is constituted by silicon oxide.
The first electric conductor is constituted by an electrically conducting film containing silicon, and provision is further made of a step of forming a silicide film on the first electric conductor exposed on the bottom in the opening. In this case, the step of forming the silicide film may include the steps of forming a metal film on the first electric conductor exposed on the bottom of the opening, and converting the metal film into a silicide through heat treatment. Further, the metal film is constituted by ruthenium, titanium or cobalt. or, the step of forming the barrier film may include the step of oxidizing the silicide film.
Further, the step of forming the first electric conductor may include the steps of forming an opening in the first insulating film, forming an electrically conducting connection member comprising silicon as a main component in the opening, and forming a silicide film on the electrically conducting connection member. In this case, the silicide film is constituted by ruthenium silicide, titanium silicide or cobalt silicide. Or, the step of forming the barrier film includes the step of oxidizing the surface of the first electric conductor exposed on the bottom of the opening.
Further, the step of forming the barrier film may include the step of forming the barrier film in the opening by a sputtering method or a CVD method. In this case, the barrier film is constituted by titanium nitride, tungsten nitride, tungsten nitride silicide, titanium nitride silicide or tantalum nitride silicide.
Further, the step of forming the first electrode may include the steps of forming a first metal film in the opening by a sputtering method, and forming a second metal film on the first metal film by a CVD method. In this case, the first and second metal films can be constituted by ruthenium or platinum. Or, in forming the first electrode, the thicknesses of the first and second metal films may be so adjusted as to reflect the shape of a dent of the opening such that the dent-remains in the upper surface thereof, and the dielectric film and the second electrode may be formed on the first electrode that includes an inner wall of the dent.
Provision is further made of the step of exposing the side walls of the first electrode by removing, by etching, the second insulating film surrounding the first electrode under a condition such that the rate of etching the second insulating film is larger than the rate of etching the first insulating film, and the dielectric film is formed even on the exposed side wall of the first electrode. Further, the step of forming the dielectric film includes the step of heat treatment for crystallizing the dielectric film.
Further, provision is made of the step of heat-treating the dielectric film in a nonoxidizing atmosphere prior to the step of heat-treating the dielectric film in an oxidizing atmosphere. In this case, the dielectric film is constituted by a tantalum oxide film, and the heat-treating temperature is in a range of from 500 to 750xc2x0 C.
Further, the step of forming the dielectric film may include the steps of forming a tantalum oxide film on the first electrode, heat-treating the tantalum oxide film in a nonoxidizing atmosphere, and forming a second dielectric film on the tantalum oxide film after the heat treatment. In this case, the second dielectric film may be a tantalum oxide film or a barium strontium titanate film.
Further, the dielectric film is constituted by a laminate of plural dielectric films. Further, the dielectric film is constituted by a single-layer film or a plural-layer film of one kind or plural kinds selected from a tantalum oxide film, a titanium oxide film, a barium strontium titanate film, a barium titanate film, and a strontium titanate film. Further, the second electrode can be constituted by ruthenium or titanium nitride.
The invention is concerned with a method of producing a semiconductor integrated circuit device having a memory cell that includes a MISFET and a capacitor element on the main surface of a semiconductor substrate, comprising the steps of: forming a MISFET on the main surface of the semiconductor substrate; forming an electric conductor that electrically connects to the source and drain regions of the MISFET; forming an insulating film on the electric conductor; forming an opening in the insulating film; forming, in the opening, a lower electrode of the capacitor element having a first ruthenium film; forming, on the first ruthenium film, a dielectric film of the capacitor element having a tantalum oxide film; and forming, on the dielectric film, an upper electrode of the capacitor element having a second ruthenium film.
In this case, the step of forming the dielectric film of the capacitor element further includes the steps of heat treatment at 500 to 750xc2x0 C. in a nonoxidizing atmosphere, and heat treatment at 500 to 700xc2x0 C. in an oxidizing atmosphere or, the step of forming the dielectric film of the capacitor element includes the steps of: forming a first tantalum oxide film; heat-treating the first tantalum oxide film for crystallization; forming a second tantalum oxide film; and heat-treating the second tantalum oxide film in an oxidizing atmosphere.
The invention is concerned with a method of producing a semiconductor integrated circuit device having a memory cell that includes a MISFET and a capacitor element on the main surface of a semiconductor substrate, comprising the steps of: forming the MISFET on the main surface of the semiconductor substrate; forming a first insulating film on the MISFET; forming a first opening in the first insulating film; forming an electrically conducting connection member in the first opening; forming a second insulating film on the first insulating film; forming a second opening in the second insulating film, and forming an electrically conducting connection member on the bottom of the second opening; forming a barrier film in the second opening; forming a first metallic connection member on the barrier film in the second opening; forming a third insulating film on the second insulating film; forming a third opening in the third insulating film to expose the metallic connection member on the bottom of the third opening; forming a lower electrode in the third opening so as to be electrically connected to the source and drain regions of the MISFET through the metallic connection member, barrier film and electrically conducting connection member; forming a dielectric film on the lower electrode; heat-treating the dielectric film in an oxidizing atmosphere; and forming an upper electrode on the dielectric film.
The invention is concerned with a method of producing a semiconductor integrated circuit device having a semiconductor region and a capacitor element that includes a first electrode, a dielectric film and a second electrode on a main surface of a semiconductor substrate, comprising the steps of: forming the semiconductor region on the semiconductor substrate; forming a first insulating film on the semiconductor region; forming a first electric conductor in the first insulating film; forming a second insulating film on the first insulating film; forming an opening in the second insulating film to expose the first electric conductor on the bottom of the opening; forming a barrier film on the bottom of the opening; forming a first electrode in the opening so as to be electrically connected to the semiconductor region through the barrier film and the first electric conductor; forming a dielectric film on the first electrode in an oxidizing atmosphere; and forming a second electrode on the dielectric film.
A semiconductor integrated circuit device of this invention comprises a semiconductor region on the main surface of a semiconductor substrate, a first insulating film on the semiconductor region, a first electric conductor in the first insulating film, a second insulating film on the first insulating film, a first electrode formed in the second insulating film so as to be electrically connected to a portion of the first electric conductor, a second electrode opposed to the first electrode, and a dielectric film formed between the first electrode and the second electrode, wherein a metal silicide film is formed between the first electrode and the first electric conductor, and a barrier film is formed between the metal silicide film and the first electrode.
In this case, the metal silicide film is formed so as to be buried in the opening formed in the first insulating film. Or, the metal silicide film is formed on the surface of the first electric conductor which is self-aligned relative to the opening formed in the second insulating film and is positioned at the portion of the opening. Or, the metal silicide film may cover the bottom of the opening formed in the second insulating film.
Further, the barrier film may be formed so as to be self-aligned to the opening formed in the second insulating film, or it may be formed on the bottom only of the opening formed in the second insulating film.
Further, a semiconductor integrated circuit device of this invention comprises a semiconductor region on the main surface of a semiconductor substrate, a first insulating film on the semiconductor region, a first electric conductor in the first insulating film, a first electrode formed like a pole and which is electrically connected to a portion of the first electric conductor, a second electrode opposed to the first electrode, and a dielectric film formed between the first electrode and the second electrode, wherein a metal silicide film is formed between the first electrode and the first electric conductor, a barrier film is formed between the metal silicide film and the first electrode, the metal silicide film has either a first constitution in which it is formed so as to be buried in the opening formed in the first insulating film or a second constitution in which it is formed on the surface of the first electric conductor on a region where the first electrode and the first conductor are in contact with each other, and the barrier film has either a first constitution in which it is formed on a region where the first electrode and the first electric conductor are in contact with each other or a second constitution in which it is formed on the whole bottom surface of the first electric conductor.
In the case of the above semiconductor integrated circuit device, the metal silicide film may be any one of a ruthenium silicide (RuSi) film, a titanium silicide (TiSi) film or a cobalt silicide (CoSi) film, and the barrier film may be any one of a ruthenium silicide film, an oxide film of a titanium silicid6 film or a cobalt silicide film, or a titanium nitride (TiN) film, a tungsten nitride (WN) film, a tungsten nitride silicide (WNSi) film, a titanium nitride-silicide (TiNSi) film or a tantalum nitride silicide (TaNSi) film. Further, the. dielectric film may be a single-layer film or a plural-layer film of one kind or plural kinds selected from a tantalum oxide film, a titanium oxide film, a barium strontium titanate film, a barium titanate film and a strontium titanate film. Further, the second electrode may be constituted by ruthenium or titanium nitride.
Further, a semiconductor integrated circuit device of this invention comprises a semiconductor region on the main surface of a semiconductor substrate, a first insulating film on the semiconductor region, a first electric conductor in the first insulating film, a second insulating film on the first insulating film, a first electrode formed in the second insulating film so as to be electrically connected to a portion of the first electric conductor, a second electrode opposed to the first electrode, and a dielectric film formed between the first electrode and the second electrode, wherein a barrier film is formed between the first electrode and the first electric conductor, the barrier film being self-aligned to the opening formed in the second insulating film. In this case, the barrier film may be a silicon oxide film.
Further, a semiconductor integrated circuit device of this invention comprises a semiconductor region on the main surface of a semiconductor substrate, a first-insulating film on the semiconductor region, a first electric conductor in the first insulating film, a second insulating film on the first insulating film, a second electric conductor in the second insulating film, a first electrode electrically connected to a portion of the second electric conductor, a second electrode opposed to the first electrode, a dielectric film formed between the first electrode and the second electrode, wherein a metal silicide film is formed between the first electric conductor and the second electric conductor, the second electric conductor being formed of ruthenium. In this case, a barrier film may be formed between the metal silicide film and the second electrode.
Further, the metal silicide film may be any one of a ruthenium silicide (RuSi) film, a titanium silicide (TiSi) film or a cobalt silicide (CoSi) film, and the barrier film may be any one of a ruthenium silicide film, an oxide film of a titanium silicide or a cobalt silicide film, or a titanium nitride (TiN) film, a tungsten nitride (WN) film, a tungsten nitride silicide (WNSi) film, a titanium nitride silicide (TiNSi) film or a tantalum nitride silicide (TaNSi) film.